1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor memory device and method thereof, and more particularly to a semiconductor memory device including a memory core and method of testing thereof.
2. Description of the Related Art
A conventional semiconductor memory device may be configured to store data. A random-access memory (RAM) device of a volatile type may be configured to function as a primary or main memory device of a computer. A dynamic random-access memory (DRAM) device, which is a type of RAM device, may include a plurality of memory cells. Each memory cell may typically include a transistor and a capacitor. In order to store data, the capacitor may store an electric charge to represent a first logic level (e.g., a higher logic level or logic “1”) or a second logic level (e.g., a lower logic level or logic “0”). Because the electric charge stored in the capacitor may be discharged over a period of time, the capacitor of the memory cell may be periodically refreshed.
A memory cell of a conventional DRAM may be electrically coupled to a word line and a bit line. If the transistor of the memory cell is turned on in response to a word line enable signal, data stored in the capacitor may be outputted through the bit line, or data on the bit line may be stored in the capacitor as a form of electric charge.
A conventional semiconductor memory device may have a folded bit-line structure or an open bit-line structure. A memory cell array in a semiconductor memory device having the open bit-line structure may include an edge sub-array having a dummy bit line. The dummy bit line may not be coupled to a sense amplifier, and memory cells coupled to the dummy bit line may not store data.
FIG. 1 is a block diagram illustrating a memory core of a conventional semiconductor memory device including an edge sub-array and a driver.
Referring to FIG. 1, the conventional semiconductor memory device may include an edge sub-array 2, non-edge sub-arrays 4 and 6, sense amplifiers 8, 10, 12, 14, 16 and 18, and a driver 22. The edge sub-array 2, the non-edge sub-arrays 4 and 6, and the sense amplifiers 8, 10, 12, 14, 16 and 18 may collectively constitute a memory core. The non-edge sub-arrays 4 and 6 may include bit lines corresponding to horizontal lines, and word lines corresponding to vertical lines, respectively, and memory cells represented by dark-colored circles may be arranged at intersection points of word lines and bit lines. The edge sub-array 2 may include word lines WL1 through WL4, bit lines BL1 and BL2, and dummy bit lines DBL1 and DBL2, and memory cells represented by dark-colored circles may be arranged at intersection points of word lines and bit lines, and at intersection points of word lines and dummy bit lines. The driver 22 may drive the dummy bit lines DBL1 and DBL2 via data line 20.
Referring to FIG. 1, in a pre-charge operation mode, voltage levels of the dummy bit lines DBL1 and DBL2 may be charged to a ½ VCC via the data line 20. In a test mode, data having the second logic level (e.g., a lower logic level or logic “0”, such as a ground voltage level or VSS level) or the first logic level (e.g., a higher logic level or logic “1”, such as the VCC level) may be transferred to the dummy bit lines DBL1 and DBL2 via the data line 20.
As shown in FIG. 1, if each dummy bit line is coupled to a single data line, identical data (e.g., set to the first logic level “1” or the second logic level “0”) may be transferred to each of the dummy bit lines. Thus, it may be difficult to detect a bridge or defect occurring between a dummy bit line and a normal bit line.
FIG. 2 is a block diagram illustrating another memory core of a conventional semiconductor memory device including an edge sub-array and a driver.
Referring to FIG. 2, a dummy bit line DBL1 may be coupled to a data line 24, and a dummy bit line DBL2 may be coupled to a data line 26. In a pre-charge operation mode, voltage levels of the dummy bit lines DBL1 and DBL2 may be charged to ½ VCC via the data lines 24 and 26. In a test mode, data having logic set to the second logic level (e.g., a lower logic level or logic “0”, such as a ground voltage level or VSS level) or the first logic level (e.g., a higher logic level or logic “1”, such as the VCC level) may be transferred to the dummy bit line DBL1 via the data line 24, and data having the second logic level (e.g., a lower logic level or logic “0”, such as a ground voltage level or VSS level) or the first logic level (e.g., a higher logic level or logic “1”, such as the VCC level) may be transferred to the dummy bit line DBL2 via the data line 26. A driver 22 may drive the dummy bit line DBL1 via the data line 24, and the dummy bit line DBL2 via the data line 26.
As shown in FIG. 2, if data is applied to the bit lines via different data lines, respectively, different data may potentially be written to each memory cell coupled to a word line W1. However, a number of data lines may be configured to be the same as a number of memory cells coupled to a single word line, so as to allow data to be freely written into dummy cells. Such a configuration may increase an amount of area required on the conventional semiconductor device such that implementation may become difficult as more memory cells are added.